なぜデータバス幅は必ず1Byteにならない？

The answer to your question may differ a bit depending on whether you're referring to processor instructions to read and write to RAM, or the actual transfer operation between RAM and CPU (which would be where the bus width comes into play. The bus width for RAM <==> CPU operations depends on the hardware. For example, DDR, DDR2, and DDR3 have a width of 64 bits.)

I'm fairly sure that the article you linked isn't referring to hardware-level communication between CPU and RAM, however. Rather, it's explaining some of the common microprocessor conventions, such as how certain memory regions may not pertain directly to RAM, but rather to provide R/W access to other data or devices.

For example, you may have memory addresses that point at hardware devices, or in embedded devices that don't have advanced IPC, can allow retrieval of configuration data and system information.

Back to your question, however: it may help your understanding to look into how assembly language works. Each CPU instruction will cause memory to be manipulated, for compared, copied, or loaded into a register. Depending on the results of a comparison, different instructions will be executed. For example:

• cmp r0,#0x0 # compare the contents of register 0 with 0
• movne r0,#0x1 # if the comparison was NOT EQUAL, then store 1 in register 0
• moveq r0,#0x0 # if the comparison was EQUAL, then store 0 in register 0.

There are many CPU instructions that will abstract more complex things away, for example, ones that can do comparisons and copies of a larger memory space than one byte.

When it comes to the communications between CPU and RAM and that bus width, however, your ability to read multiple bytes of memory from RAM -> CPU in one cycle will depend on the storage used and how you interface with it. I must confess that this isn't my specialty; but it can help with understanding to differentiate between CPU instructions and CPU <==> RAM communications.